In a cellular system implementing a third generation mobile network technology compliant with the 3GPP Long Term Evolution (LTE) standard, high bit rate and latency are very restricted when compared to previous standards. The high bit rate and latency restrictions pose many challenges to developers of an LTE compliant system. In order to meet latency requirements, processing needs to be fast. For fast processing, powerful processors are needed, which increases the project budget. The powerful processors also increase power consumption. An LTE downlink (DL) has a maximum bit rate of 300 Mbps for Release-8 and Release-9 and 600 Mbps for Release-10 (LTE-ADVANCED) for a bandwidth of 20 MHz. The bit rate can be split among several mobile units (referred to as user equipment or UEs).
Referring to FIG. 1, a flow diagram 10 is shown illustrating a main function 10 of a downlink (DL) layer 1 (L1) processing scheme. The function 10 provides input to a radio frequency (RF) interface. The function 10 performs a cyclic redundancy check (CRC) process 12, a turbo coding process 14, a sub-block interleaving and rate matching process 16, a scrambling process 18, a modulation process 20, a layer mapping and precoding process 22, a resource block (RB) mapping process 24, and an inverse fast Fourier transform (IFFT) calculation process 26. The resource block mapping process 24 produces a resource grid 28. The resource grid 28 contains orthogonal frequency division multiplexed (OFDM) symbols 30. One OFDM symbol 30 is one column in the resource grid 28. The resource grid 28 contains a total of 14 columns in the case of a normal cyclic prefix (CP).
According to the 3GPP LTE standard (see section 6.4 of the 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA); Physical Channels and Modulation (Release 10), document 3GPP TS 36.211 v10.1.0) all of the processing including the resource block mapping process 24 is to be completed before the inverse fast Fourier transform (IFFT) calculation process 26 is started. According to the standard, the resource block mapping process 24 shall be completed for all UEs until the resource grid 28 is full. Only when the resource grid 28 is full can the IFFT calculation process 26 be performed on the OFDM symbols 30. The latency for the downlink data processing is measured from the generation of the CRC bit by the CRC process 12 until the first OFDM symbol 30 is ready for presentation to the RF interface (i.e., the inverse fast Fourier transform (IFFT) calculation process 26 has been performed on the first OFDM symbol). Implementation according to the 3GPP LTE standard requires a lot of processing for the first OFDM symbol to be ready for the RF interface, because all the processing for all of the UEs needs to be completely finished before starting the inverse fast Fourier transform (IFFT) calculation process 26.
It would be desirable to implement a method for reducing latency on LTE DL implementation.